DTT4C08 is an 8-bit 8K intelligent CPU card chip with low power consumption, high performance, repeatable FLASH program memory and 8K EEPROM data memory. It is designed with Top-Down design method.
1 Introduction to DTT4C08 chip
1.1 DTT4C08 pin definition (module status)
Its pin definition and layout are shown in Figure 1.
1.2 Basic hardware structure
Central processing CPU, 16K byte program memory FLASH, 256 bytes data storage SRAM, EEPROM 8K data memory EEPROM. DTT4C08 chip uses FLASH technology to make FLASH memory with fast programming speed, short erasing time and small area, and has corresponding control, interface and anti-attack circuit, which is safer, more open and more flexible. DTT4C08 The chip CPU instruction set is fully compatible with the MCS-51.
1.3 DTT4C08 chip other instructions
(1) 8K bytes of EEPROM data memory support page operations and byte operations;
(2) 256-byte internal SRAM unit that supports bit addressing;
(3) With a clock frequency detector. When the external clock is stopped, the FLASH is placed in the stand by state, and the EEPROM and SRAM are stopped to reduce power consumption.
2 DTT4C08 based smart card application development method
2.1 chip operating system software design method
The following is a brief description of the application development of the DTT4C08 software based on the telecom smart card operating system (COS) development process. The external device is used to perform the operation. After the card is powered on, the parameter initialization is first performed, and the ATR is sent to the mobile terminal. The card and the mobile terminal ME perform a transmission protocol agreement, and then start receiving command data and performing data analysis, and then transfer the corresponding command according to the analysis result. The subroutine entry and execution of the command, the card is sent to the mobile terminal to respond after the command ends. When an instruction execution process ends, the card restarts receiving data and executes the next instruction.
The flow chart of the telecom smart card COS main control program is shown in Figure 2.
2.2 chip operating system software debugging environment
After the chip operating system code is completed, the software simulation test can be carried out by using the "integrated debugging environment + reader simulator" software simulation system recommended by Datang Microelectronics. The simulation system covers the simulation requirements of the smart card application development for the simulator, and can simulate the I/O input and output of the ISO7816 standard, which is beyond the software simulation in the usual sense. After the simulation of the entire chip operating system, the program card can be downloaded, and the real "card" is used as the "debug carrier". Make the development process exactly the same as the actual application environment.
Figure 3 shows the simulation debugging of the DTT4C08 chip through a microcomputer.
3 A design method for the transfer interface application
The card (DTT4C08 chip) receives the command data of the ME to perform data analysis, and according to the analysis result, it is transferred to the corresponding command subroutine entry and executes the command. The information structure of the command data, that is, the application protocol data unit (APDU) is as shown in FIG.
The CLA is the command category, and the value is “A0â€. When CLA=FF, it is the header of the PTS process; the INS is the instruction code, which is used to separate the commands. The ME serially transmits the command data to the card through the I/O bidirectional data line in the order of FIG. 4, and the card temporarily stores CLA, INS, P1, P2, and P3 in R3, R4, R5, R6, and R7, respectively. A specified contiguous unit stored in RAM. The simplest command diversion judgment procedure is as follows:
CJNE R4, #0A4H, NEXT_INS01; determine the specific command through INS
LJMP SELECT ; turn to SELECT instruction handler
NEXT_INS01: CJNE R4, #0F2H, NEXT_INS02
LJMP STATUS ; turn to STATUS instruction handler
NEXT_INS02: CJNE R4, #0B0H, NEXT_INS03
LJMP READ_DINARY ; to the READ_BINARY instruction handler
NEXT_INS03: ......
NEXT_INS34: CJNE R4, #14H, NEXT_INS22
LJMP TERMINAL_RESPONSE
; to TERMINAL_RESPONSE instruction handler
NEXT_INS35: Error handling
In addition to the standard GSM command, plus the scatter processing of additional commands such as SIM card issuance and debugging, the card needs to process at least 35 instructions (210 bytes), which occupies more program space. This article uses the stack and subroutine return instructions to determine the design of the scatter entry by looking up the table, subtly obtaining the instruction processing entry address, and the scatter program only needs 131 bytes, which greatly saves program space. The more commands you need to process, the more program space you save.
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